Heterogeneous Computing for Artificial Intelligence Applications (RESCHIP4EU)

This course, delivered by the University of Turku in Finland, introduces the principles and practical techniques of heterogeneous computing, focusing on systems that combine CPUs and FPGAs to accelerate artificial intelligence (AI) and machine learning workloads. Students will gain hands-on experience developing and optimising FPGA-based AI accelerators. 

About this course

In today’s era of rapidly growing AI workloads and data-intensive applications, heterogeneous computing has become essential for achieving high performance and energy efficiency. This course introduces the principles and practical techniques of heterogeneous computing, focusing on systems that combine CPUs and FPGAs to accelerate artificial intelligence (AI) and machine learning workloads. Students will explore how computation is distributed across heterogeneous architectures, how to design and implement hardware accelerators, and how to integrate them with CPUs using modern tools and frameworks. Through a combination of theory, design labs, and project-based learning, participants will gain hands-on experience developing FPGA-based AI accelerators, optimising data movement and parallelism, and deploying end-to-end AI inference pipelines.

Course structure

• Understand the architecture and design principles of heterogeneous computing systems.  
• Develop FPGA hardware accelerators for compute-intensive tasks. Implement and integrate AI inference kernels between CPU and FPGA.  
• Optimize performance, latency, and energy efficiency in heterogeneous platforms.  
• Use industry tools (such as Xilinx Vitis, Intel OneAPI, or OpenCL) for hardware–software co-design.  
• Evaluate trade-offs among CPU, GPU, and FPGA acceleration for AI workloads. 

Learning outcomes

Upon successful completion of this course, students will be able to:

• Describe and analyse the design trade-offs in heterogeneous architectures.
• Implement and optimize FPGA-based accelerators for AI tasks.
• Partition and co-schedule workloads across CPU and FPGA.
• Use hardware–software co-design workflows to accelerate neural network inference.
• Evaluate acceleration performance using metrics like throughput, latency, and power. 

Further details 

This course is developed within the framework of the RESCHIP4EU project, with the support of the Digital Europe Programme of the European Union. More information on the course is available on the project's website via here.